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Low-power CMOS with subvolt supply voltages

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1 Author(s)
Stan, M.R. ; Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA

We first present a circuit taxonomy along the space and time dimensions, which is useful for classifying generic low-power techniques, followed by an analysis of optimal power supply and threshold voltages and transistor sizing for minimizing the energy-delay product of a class of complementary metal-oxide-semiconductor (CMOS) digital circuits.

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:9 ,  Issue: 2 )