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A built-in self-test method for diagnosis of synchronous sequential circuits

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2 Author(s)
Pomeranz, I. ; Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; Reddy, S.M.

We propose an approach for built-in fault diagnosis of synchronous sequential circuits. The proposed approach distinguishes faults based on their detection by modified versions of a fault detection test sequence generated on-chip. The modified versions are defined by one-bit-wide auxiliary sequences, also generated on-chip. The auxiliary sequences indicate which test vectors of the fault detection test sequence need to be applied to the circuit. Experimental results presented indicate that the proposed on-chip test generation method is effective in achieving high levels of diagnostic-resolution.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:9 ,  Issue: 2 )

Date of Publication:

April 2001

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