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A network processor architecture for flexible QoS control in very high-speed line interfaces

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2 Author(s)
Shimonishi, H. ; Comput. & Commun. Media Res., NEC Corp., Japan ; Murase, T.

We developed a network processor architecture that can be used for very high-speed line interfaces of carrier-class backbone routers and switches. Because advanced queuing and packet scheduling mechanisms are implemented as a software routine without the need for any special hardware components, the architecture provides a flexible QoS control mechanism and enables effective header handling

Published in:

High Performance Switching and Routing, 2001 IEEE Workshop on

Date of Conference: