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On scheduling using parallel input-output queued crossbar switches with no speedup

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3 Author(s)
S. S. Mneimneh ; MIT, Cambridge, MA, USA ; V. Sharma ; Kai-Yeung Siu

We propose an efficient parallel switching architecture (PSA) that requires no speedup and guarantees bounded delay. Our architecture consists of κ crossbar switches operating in parallel under the control of a single scheduler, with κ being independent of N the number of inputs and outputs of the PSA. Arriving traffic is demultiplexed (spread) over the κ identical crossbar switches, switched to the correct output, and multiplexed (combined) before departing from the parallel switch. We show that by using an appropriate demultiplexing strategy at the inputs and by applying the same matching at each of the κ parallel crossbar switches during each slot, our scheme guarantees that the cells of a flow can be read in FIFO order from the output queues of the crossbar switches, thus eliminating the need for cell resequencing. Further, by allowing the PSA scheduler to examine the state of only the first of the κ parallel switches, our scheme also reduces considerably the amount of state information required at the scheduler. The scheduling algorithms that we develop are based on existing practical scheduling algorithms for crossbar switches, and have an additional communication complexity that is optimal up to a constant factor. Our approach also provides a way to build a high capacity switch/router that can support line rates that are higher than the speed at which the parallel switches themselves operate

Published in:

High Performance Switching and Routing, 2001 IEEE Workshop on

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