By Topic

Parallel packet forwarding architecture using ATM switch core for scalable performance

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
K. Shiomoto ; NTT Network Service Syst. Labs., Tokyo, Japan ; M. Omotani ; M. Uga ; S. Shimizu

This paper proposes a label switch router architecture using ATM switch core. Hardware-based forwarding engines are attached to the switch core in a scalable fashion in the proposed label switch router. Dimensioning the number of forwarding engines is proposed to achieve scalable performance. An ATM virtual circuit is used as label switched path in the MPLS network. Traffic management and OAM capabilities are applied to achieve carrier-grade network control for the network infrastructure the next generation Internet is to provide

Published in:

High Performance Switching and Routing, 2001 IEEE Workshop on

Date of Conference:

2001