By Topic

The design of a one megabit non-volatile M-R memory chip using 1.5×5 μm cells

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Pohm, A.V. ; Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA ; Huang, J.S.T. ; Daughton, J.M. ; Krahn, D.R.
more authors

A 106-bit chip has been designed using 1.5-μm magnetoresistive double-layer memory elements and bipolar circuitry. The bipolar circuitry is based on nominal 1.25-μm optical lithography. The total chip area of the design is 8.5 mm×9.5 mm. To enhance the signal-to-noise ratio, multiple reads are used with the nondestructive readout cells. Design read time is 3 μs. Design write time is 0.2 μs. The design includes three redundant, fuse-selectable sense lines for each group of 32 sense lines. If the bit failure rate is 0.0005 or less, yield loss for the 106-bit chip due to sense line failure is less than 19%. With improved lithography, elements as small as 0.75 μm×2.5 μm could be made from the material

Published in:

Magnetics, IEEE Transactions on  (Volume:24 ,  Issue: 6 )