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Precedence-based, preemptive, and power-constrained test scheduling for system-on-a-chip

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2 Author(s)
Iyengar, V. ; Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA ; Chakrabarty, K.

Test scheduling is a major problem in system-on-a-chip (SOC) test automation. We present an integrated framework that addresses several important test scheduling problems. We first present efficient techniques to determine optimal SOC test schedules with precedence constraints, i.e., schedules that preserve desirable orderings among tests. We then present a new algorithm that uses preemption to obtain optimal test schedules in polynomial time. Finally, we present a new method for determining optimal power-constrained schedules. Experimental results for a representative SOC show that test schedules can be obtained in reasonable CPU time for all cases

Published in:

VLSI Test Symposium, 19th IEEE Proceedings on. VTS 2001

Date of Conference:

2001

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