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High-voltage stress test paradigms of analog CMOS ICs for gate-oxide reliability enhancement

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2 Author(s)
Khalil, M.A. ; Dept. of Electr. & Comput. Eng., Michigan State Univ., East Lansing, MI, USA ; Chin-Long Wey

This paper presents the first-ever research on high-voltage stress of analog circuits to enhance their oxide reliability and to reduce the manufacturing cost. The emphasis of this paper is placed on how to properly stress analog circuits and the development of efficient algorithms for generating stress vectors that meet the stress coverage requirement within a feasible stress time

Published in:

VLSI Test Symposium, 19th IEEE Proceedings on. VTS 2001

Date of Conference:

2001