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Multiple scan chain design for two-pattern testing

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2 Author(s)
Polian, I. ; Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany ; Becker, B.

Non-standard fault models often require the application of true-pattern testing. A fully-automated approach for generating a multiple scan chain-based architecture is presented so that two-pattern test sets generated for the combinational core can be applied to the sequential circuit. Test time and area overhead constraints are considered

Published in:

VLSI Test Symposium, 19th IEEE Proceedings on. VTS 2001

Date of Conference:

2001

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