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Application of output prediction logic to differential CMOS

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3 Author(s)
Kio, S. ; Washington Univ., Seattle, WA, USA ; McMurchie, L. ; Sechen, C.

We apply the output prediction logic (OPL) technique to the differential CMOS logic family. Including the effects of process, voltage and temperature (PVT) variations, we show that OPL differential CMOS is more than 40% faster than the single-rail OPL-dynamic logic family, and nearly 5 times faster than optimized static CMOS. We also demonstrate an OPL-differential 64:2 compressor that is 37% faster than the OPL-dynamic version. Finally, we show that OPL-differential is nearly twice as fast as differential domino

Published in:

VLSI, 2001. Proceedings. IEEE Computer Society Workshop on

Date of Conference:

May 2001

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