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Power modeling and low-power design of content addressable memories

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3 Author(s)
Ilion Yi-Liang Hsiao ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Ding-Hao Wang ; Chein-Wei Jen

Content addressable memory (CAM), a high-performance lookup engine in many systems, is so power-consuming that any saving becomes very significant in the whole system. This paper derives power models for four low-power CAMs from the fCV2 base model. CAM has three major power-sinking sources: evaluation power, input transition power and clocking power, all of them are discussed in this paper. After that, a new low-power CAM design is proposed here. Its implementation under 0.35-μm process operates at 83.3 MHz with power performance metric as 45.5 fJ/bit/search or equivalently 372 mJ/bit/search/m2 for random inputs. Two modified circuit structures for binary static CAM cells are also proposed. We have proved that under most conditions cell layout is smaller by this modification

Published in:

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on  (Volume:4 )

Date of Conference:

6-9 May 2001