ESD protection design in a 0.18-/spl mu/m salicide CMOS technology by using substrate-triggered technique

A novel substrate-triggered technique, as comparing to the traditional gate-driven technique, is proposed to effectively improve ESD (electrostatic discharge) robustness of IC products. The on-chip ESD protection circuits designed with the substrate-triggered technique for input, output and power pads have been fabricated and verified in a 0.18-/spl mu/m salicide CMOS process. The HBM ESD level of the ESD protection NMOS with a W/L of 300 /spl mu/m/0.3 /spl mu/m can be improved from the original 0.8 kV to become 3.3 kV by this substrate-triggered technique.