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ESD protection design in a 0.18-μm salicide CMOS technology by using substrate-triggered technique

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3 Author(s)
Ming-Dou Ker ; Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Tung-Yang Chen ; Chung-Yu Win

A novel substrate-triggered technique, as comparing to the traditional gate-driven technique, is proposed to effectively improve ESD (electrostatic discharge) robustness of IC products. The on-chip ESD protection circuits designed with the substrate-triggered technique for input, output and power pads have been fabricated and verified in a 0.18-μm salicide CMOS process. The HBM ESD level of the ESD protection NMOS with a W/L of 300 μm/0.3 μm can be improved from the original 0.8 kV to become 3.3 kV by this substrate-triggered technique

Published in:

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on  (Volume:4 )

Date of Conference:

6-9 May 2001