Low power techniques for flash memories

Low power digital techniques to reduce power dissipation during write operations are implemented in 3V-only, 1M cells, NOR-flash memory. The test chip is fabricated in 0.5 /spl mu/m, 3-metal, triple-cell CMOS technology. Measurement results show that these methods combined with conventional low current programming algorithms allow a reduction in power consumption of 40% with a 20% reduction of overhead in total chip area.