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Low power techniques for flash memories

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3 Author(s)
Canegallo, R. ; Innovative Syst. Design Group, STMicroelectron., Milan, Italy ; Dozza, D. ; Guerrieri, R.

Low power digital techniques to reduce power dissipation during write operations are implemented in 3V-only, 1M cells, NOR-flash memory. The test chip is fabricated in 0.5 μm, 3-metal, triple-cell CMOS technology. Measurement results show that these methods combined with conventional low current programming algorithms allow a reduction in power consumption of 40% with a 20% reduction of overhead in total chip area

Published in:

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on  (Volume:4 )

Date of Conference:

6-9 May 2001