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Customizable DSP architecture for ASIP core design

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2 Author(s)
Y. Bajot ; Lab. LIP6/ASIM, Paris VI Univ., France ; H. Mehrez

We present in this paper a configurable DSP architecture and its associated software framework intended to be used in ASIP core design. This architecture aims to speed up the execution of a well-defined target application and minimize the hardware cost. It is based on a configurable and modular model that makes the most of intrinsic ILP of the application by the use of specialized functional units and VLIW instructions. Implementation results of a complex application, the GSM EFR encoder algorithm, shows the efficiency of the customized architecture

Published in:

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on  (Volume:4 )

Date of Conference:

6-9 May 2001