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A CMOS clock and data recovery with two-XOR phase-frequency detector circuit

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2 Author(s)
Jin-Ku Kang ; Dept. of Electr. & Comput. Eng., Inha Univ., Inchon, South Korea ; Dong-Hee Kim

This paper describes a 1.0 Gbps Clock and Data Recovery circuit with a simple PFD structure. The proposed circuit is based on a single loop controlled by a Phase Frequency Detector (PFD) which has two-XOR gates. The VCO composed of four differential buffer stages generates eight differential clocks each spaced by 45°. The PFD generates the VCO control signal by comparing two different phase clocks and input data. The circuit operates on 800 Mbps to 1.2 Gbps data rate under 2.5 V supply using 0.25 μm-CMOS HSPICE simulation. The circuit is under fabrication. The measured results are presented

Published in:

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on  (Volume:4 )

Date of Conference:

6-9 May 2001