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An optimization-based low-power voltage scaling technique using multiple supply voltages

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2 Author(s)
Yi-Jong Yeh ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Sy-Yen Kuo

In this paper, we proposed a voltage scaling technique with multiple supply voltages for low-power designs. We considered the path sensitization as well as releasing the clustering constraint applied in the CVS (Clustered Voltage Scaling) technique. Our technique operates the gates with the lowest feasible supply voltages and then uses an existing path selection algorithm for optimization. Experiments are conducted on the ISCAS85 benchmarks and the results show that about 20% power on average can be further reduced by our technique in comparison with the CVS technique

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Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on  (Volume:5 )

Date of Conference: