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Fast low-power characterization of arithmetic units in DSM CMOS

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3 Author(s)
Dhaou, I.B. ; Electron. Syst. Design Lab., R. Inst. of Technol., Stockholm, Sweden ; Money, N. ; Tenhunen, H.

New technique for low-power characterization of arithmetic units in Deep-Submicron (DSM) CMOS technology is proposed. The core of this technique is based on a proper transformation of the input pattern in order to improve fit and prediction of the power consumption. The transformation is also useful in reducing the complexity associated with the characterization process without sacrificing the accuracy of the estimators. In this paper, the entropy of the input pattern is proposed as a transformation technique. An algorithm, called LP-DSM, for library characterization based on the entropy of the input pattern is derived. The LP-DSM takes into account the glitch power consumption. LP-DSM algorithm has been used to characterize the power consumption of several arithmetic units implemented, using full-custom design, in 0.3 μm, 3.3 V CMOS process. Under the real delay model, the extensive numerical results have showed that the average error of LP-DSM is less than 16% compared to Spice results. Also, the results have shown that LP-DSM is very robust to the variations in the statistics of the input pattern

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Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on  (Volume:5 )

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