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Low power driven re-synthesis algorithm for heterogeneous FPGA under delay constraint

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4 Author(s)
Po-Xun Chiu ; Dept. of Inf. & Comput. Eng., Chung Yuan Christian Univ., Chung Li, Taiwan ; Yu-Chung Lin ; Yi-Ling Hsieh ; Tsai-Ming Hsieh

In this paper, we propose a low power driven re-synthesis algorithm for LUT-based heterogeneous FPGA under delay constraint. We start with a delay optimal solution by using HeteroMap. The solution is then processed to reduce the power consumption and the circuit delay is held. Experimental results show that power consumption of the original mapping solution has been reduced by 15.02%. In addition, our algorithm can further reduce the power consumption when the delay constraint is relaxed

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Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on  (Volume:5 )

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