Cart (Loading....) | Create Account
Close category search window
 

Automatic clock tree design with IPs in the system

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Li, W. ; Dept. of Electr. Eng., Texas Univ., Dallas, TX, USA ; Zhou, D. ; Haksu Kim ; Zeng, X.

A clock distribution methodology is presented for realizing the prespecified clock arriving time often occurring in the reusable block based design environment. In this strategy, not only the planar clock routing and buffer insertion are carried out simultaneously to minimize the total wire length and the clock skew, a full waveform simulation is used to ensure the signal integrity necessary for high-speed VLSI. Our experimental results demonstrate that the proposed method achieves a good circuit performance

Published in:

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on  (Volume:5 )

Date of Conference:

2001

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.