An efficient balanced truncation realization algorithm for interconnect model order reduction

This paper presents an efficient model order reduction method for VLSI interconnect that is based on balanced truncation realization. Our scheme uses both predominant controllability and observability spaces, and shows that there is no need to solve the whole Lyapunov equation for controllability and observability grammians before obtaining approximation to their predominant spaces. The linear order reduction algorithm can be achieved by extending the O(n) Krylov Subspace Oblique Projection method.