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Cycle time optimization by timing driven placement with simultaneous netlist transformations

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4 Author(s)
Hartje, H. ; Fault Tolerant Comput. Group, Potsdam Univ., Germany ; Neumann, I. ; Stoffel, D. ; Kunz, W.

We present new concepts to integrate logic synthesis and physical design. Our methodology uses general Boolean transformations as known from technology-independent synthesis, and a recursive bi-partitioning placement algorithm. In each partitioning step, the precision of the layout data increases. This allows effective guidance of the logic synthesis operations for cycle time optimization. An additional advantage of our approach is that no complicated layout corrections are needed when the netlist is changed

Published in:

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on  (Volume:5 )

Date of Conference:

2001