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Deriving accurate ASIC cell fault models for VITAL compliant VHDL simulation

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3 Author(s)
Shaw, D. ; Dept. of Electr. & Comput. Eng., R. Mil. Coll. of Canada, Kingston, Ont., Canada ; Al-Khalili, D. ; Rozon, C.

This paper introduces a system for deriving accurate, technology specific fault models using analog defect simulation. It is implemented by a new software tool that provides a push-button solution for the tedious task of obtaining accurate ASIC cell defect to fault mappings. After completion of the cell defect analysis, the tool generates VITAL compliant, defect-injectable, VHDL cell models. These provide an efficient means to conduct accurate fault simulation of ASIC standard cell designs

Published in:

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on  (Volume:5 )

Date of Conference:

2001