Referenced Items are not available for this document.
This paper presents a novel power profile manipulation technique which improves the test application time of existing power constrained test scheduling algorithms. This is achieved by test sequence reordering and rotation combined with a new power approximation model. Experiments using benchmark circuits show that use of this technique can lead to savings up to 25% in test time
Published in:
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
(Volume:5
)
Date of Conference: 2001
- Page(s):
- 251 - 254 vol. 5
- Meeting Date :
- 06 May 2001-09 May 2001
- Print ISBN:
- 0-7803-6685-9
- INSPEC Accession Number:
- 7036360
- Conference Location :
- Sydney, NSW
- Digital Object Identifier :
- 10.1109/ISCAS.2001.922032
- Product Type:
- Conference Publications
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