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Power constrained test scheduling using power profile manipulation

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3 Author(s)
P. M. Rosinger ; Dept. of Electron. & Comput. Sci., Southampton Univ., UK ; B. M. Al-Hashimi ; N. Nicolici

This paper presents a novel power profile manipulation technique which improves the test application time of existing power constrained test scheduling algorithms. This is achieved by test sequence reordering and rotation combined with a new power approximation model. Experiments using benchmark circuits show that use of this technique can lead to savings up to 25% in test time

Published in:

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on  (Volume:5 )

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