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Scheduling tests for low power built-in self-test

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2 Author(s)
Schuele, T. ; Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany ; Stroele, A.P.

During test, circuits are exposed to an increased switching activity which can rise severe hazards to their reliability due to excessive power consumption and heat dissipation. We consider the problem of scheduling tests under peak power constraints such that the total energy consumption is minimized. The proposed method takes into account switching activity which occurs in overlapping regions of the subcircuits under test by means of a hierarchical approach to power estimation

Published in:

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on  (Volume:5 )

Date of Conference:

2001