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CMOS imager with charge-leakage compensated frame difference and sum output

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5 Author(s)
B. Pain ; Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA ; S. Seshadri ; M. Ortiz ; C. Wrigley
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This paper presents a new technique for implementing a low-power CMOS imager with simultaneous on-chip computation of the difference and sum of two successive frames. Existing difference imagers are susceptible to errors due to collection (by the sense element and in-pixel storage node) of photo-generated charge that diffuses from the photo-active pixel area during integration of the second frame. This leakage cannot be removed in post-processing without frame rate reduction and additional frame memory penalties to readout and store the original frames. Our proof-of-concept imager uses a new unbalanced differential signal chain to provide 17 fold reduction in leakage error in the frame-difference output. The resulting residual error is <1.5% of the actual frame difference value, over >100x illumination range. Error reduction is achieved without noticeable fixed-pattern-noise (FPN) or random noise in the image, preserving high image quality. Power dissipation in the 256×256 imager is measured to be only 18 mW

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Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on  (Volume:5 )

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