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A design of LUT-array-based PLD and a synthesis approach based on sum of generalized complex terms expression

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5 Author(s)
Tsutsui, H. ; Dept. of Commun. & Comput. Eng., Kyoto Univ., Japan ; Hiwada, K. ; Izumi, T. ; Onoye, T.
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In this paper, an architecture of LUT-array-based PLD and a synthesis approach based on sum of generalized complex terms (SGCTs) expression are proposed. We formulate logic synthesis and layout for the LUT array into SGCT minimization so that the SGCT approach successfully merges these two synthesis stages. An SGCT generation procedure from an incompletely specified function is also presented. Experimental results demonstrate that the numbers of terms needed by our approach to map benchmark circuits into 2-LUT arrays and 3-LUT arrays are reduced to 70.7% and 85.1% on average of those by the existing approach, respectively

Published in:

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on  (Volume:5 )

Date of Conference:

2001