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A low power 10 bit, 80 MS/s CMOS pipelined ADC at 1.8 V power supply

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4 Author(s)
Yong-In Park ; Data Converter Group, Texas Instrum. Inc., Dallas, TX, USA ; S. Karthikeyan ; F. Tsay ; E. Bartolome

CMOS process technology has been moving rapidly towards finer geometry for higher system integration faster clock frequencies and lower power consumption. With deep sub-micron CMOS transistors, the voltage supply has been reduced from 5.0 V to 3.3 V and even to 1.8 V. Lower supply voltage presents a major challenge to analog circuit design due to mostly reduced dynamic range and lower SNR and SINAD. While 1.5 V ADC has been designed at 10-bit resolution, the performance has been limited to less than 20 Msps. Other 10-bit, 100 MS/s ADCs have been demonstrated, yet with higher supply voltage and higher power consumptions. This paper introduces a design that addresses the issues of 1.8 V supply in a 10-bit 80 MS/s pipeline ADC implemented in a 0.18 μm CMOS process. The total power consumption of the chip is only 80 mW, which is the least compared to other ADCs with similar performance reported in the literature to date

Published in:

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on  (Volume:1 )

Date of Conference:

6-9 May 2001