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A low voltage 8-bit, 40 MS/s switched-current pipeline analog-to-digital converter

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3 Author(s)
Hughes, J.B. ; Philips Res. Lab., Redhill, UK ; Mec, M. ; Donaldson, W.

An 8-bit, 40 MS/s, switched current pipeline analog-to-digital converter is presented. It employs a multiplexed architecture with tapered bit stage design and enhanced two-step circuit techniques. Implemented in a 3.3 V, 0.35 μm CMOS process but operating internally from a 1.9 V supply, it achieves 6.4 effective number of bits and a resolution bandwidth of 5 MHz with a dissipation of 60 mW

Published in:

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on  (Volume:1 )

Date of Conference:

6-9 May 2001