Referenced Items are not available for this document.
An 8-bit, 40 MS/s, switched current pipeline analog-to-digital converter is presented. It employs a multiplexed architecture with tapered bit stage design and enhanced two-step circuit techniques. Implemented in a 3.3 V, 0.35 μm CMOS process but operating internally from a 1.9 V supply, it achieves 6.4 effective number of bits and a resolution bandwidth of 5 MHz with a dissipation of 60 mW
Published in:
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
(Volume:1
)
Date of Conference: 6-9 May 2001
- Page(s):
- 572 - 575 vol. 1
- Meeting Date :
- 06 May 2001-09 May 2001
- Print ISBN:
- 0-7803-6685-9
- INSPEC Accession Number:
- 6971439
- Conference Location :
- Sydney, NSW
- Digital Object Identifier :
- 10.1109/ISCAS.2001.921920
- Product Type:
- Conference Publications
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