Referenced Items are not available for this document.
This paper describes a technique for digital error correction in pipelined analog-digital converters. It makes use of a slow, high resolution ADC in conjunction with an LMS algorithm to perform error correction in the background during normal conversion. The algorithm has been shown to correct for errors due to capacitor ratio mismatch, finite amplifier gain and charge injection within the same framework
Published in:
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
(Volume:1
)
Date of Conference: 6-9 May 2001
- Page(s):
- 408 - 411 vol. 1
- Meeting Date :
- 06 May 2001-09 May 2001
- Print ISBN:
- 0-7803-6685-9
- INSPEC Accession Number:
- 6971398
- Conference Location :
- Sydney, NSW
- Digital Object Identifier :
- 10.1109/ISCAS.2001.921879
- Product Type:
- Conference Publications
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