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Analog VLSI spiking neural network with address domain probabilistic synapses

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3 Author(s)
Goldberg, D.H. ; Dept. of Electr. & Comput. Eng., Johns Hopkins Univ., Baltimore, MD, USA ; Cauwenberghs, G. ; Andreou, A.G.

We present an analog VLSI address-event transceiver containing an array of integrate-and-fire neurons and a scheme for implementing a reconfigurable neural network with probabilistic synapses. Neural “spikes” are transmitted through address-event representation-the address of the sending neuron is communicated through an asynchronous request and acknowledgment cycle. Continuous-valued synaptic weights are implemented by probabilistically routing address events. Results from a prototype system with 1024 analog VLSI integrate-and-fire neurons, each with up to 128 probabilistic synapses, demonstrate these concepts in an image processing application

Published in:

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on  (Volume:3 )

Date of Conference:

6-9 May 2001