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A compatible DCT/IDCT architecture using hardwired distributed arithmetic

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7 Author(s)
Dae Won Kim ; Sch. of Electr. Eng., Kyungpook Nat. Univ., Taegu, South Korea ; Taek Won Kwon ; Jung Min Seo ; Jae Kun Yu
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In this paper, we evaluate the hardware implementation method of general DCT/IDCT compatible architecture with minimum resource and high speed. We proposed and implemented the hardwired DA (distributed arithmetic) method with radix-2 multibit coding for the minimum resource, and we used symmetric transpose memory for high speed. Generally, IDCT procedure consists of two ID-IDCT procedures and one transpose. This architecture shows some resources of IDCT core are reusable for DCT process. We propose a general scheme for the processing element of which the gate count is 8.6 K for DCT and 9.2 K for IDCT, through Verilog HDL simulation in 0.65 um SOG technology. Also, we verify that the simulation results using Matlab are acceptable for IEEE Std 1180-1990

Published in:

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on  (Volume:2 )

Date of Conference:

6-9 May 2001