System Maintenance Notice:
Single article purchases and IEEE account management are currently unavailable. We apologize for the inconvenience.
By Topic

The COBRA-ABS high-level synthesis system for multi-FPGA custom computing machines

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
3 Author(s)
Duncan, A.A. ; Dept. of Eng., Aberdeen Univ., UK ; Hendry, D.C. ; Gray, P.

This paper describes the column oriented butted regular architecture-algorithmic behavioral synthesis (COBRA-ABS) high-level synthesis tool which has been designed to synthesize DSP algorithms, specified in C, onto multi-field programmable gate array (FPGA) custom computing machines (FCCMs). COBRA-ABS performs synthesis using a new simulated annealing-based methodology, which maps the specified behavior into a four-dimensional (4-D) space and then optimizes the implied architecture. COBRA-ABS synthesizes custom very long instruction word (VLIW) style architectures partitioned across the FPGAs of the FCCM and has been used to compile C algorithms down to FPGA configuration bit-streams. This paper describes the tool and synthesis concepts and presents simulation results from a number of synthesized fast Fourier transform (FFT) related algorithms.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:9 ,  Issue: 1 )