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A bitstream reconfigurable FPGA implementation of the WSAT algorithm

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6 Author(s)
Leong, P.H.W. ; Dept. of Comput. Sci. & Eng., Chinese Univ. of Hong Kong, Shatin, China ; Sham, C.W. ; Wong, W.C. ; Wong, H.Y.
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A field programmable gate array (FPGA) implementation of a coprocessor which uses the WSAT algorithm to solve Boolean satisfiability problems is presented. The input is a SAT problem description file from which a software program directly generates a problem-specific circuit design which can be downloaded to a Xilinx Virtex FPGA device and executed to find a solution. On an XCV300, problems of 50 variables and 170 clauses can be solved. Compared with previous approaches, it avoids the need for resynthesis, placement, and routing for different constraints. Our coprocessor is eminently suitable for embedded applications where energy, weight and real-time response are of concern.

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:9 ,  Issue: 1 )