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Design considerations for databus charge recovery

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4 Author(s)
B. Bishop ; Georgia Univ., Athens, GA, USA ; V. Lyuboslavsky ; N. Vijaykrishnan ; M. J. Irwin

The charge recovery databus is a scheme which reduces energy consumption through the application of adiabatic circuit techniques. Previous work gives a solid theoretical analysis of this scheme, including quantitative data assuming random bus values. We extend this earlier work by presenting a quantitative analysis of the charge recovery databus using 15 benchmarks and four high level bus coding schemes. We show that a very simple implementation of the charge recovery databus is capable of reducing average energy consumption by 28% beyond traditional high-level bus encoding techniques. In addition, we examine delay and energy consumption in the added hardware.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:9 ,  Issue: 1 )