By Topic

Critical area computation for missing material defects in VLSI circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Papadopoulou, E. ; IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

We address the problem of computing critical area for missing material defects in a circuit layout. The extraction of critical area is the main computational problem in very large scale integration yield prediction. Missing material defects cause open circuits and are classified into breaks and via blocks. Our approach is based on the L medial axis of polygons and the weighted L Voronoi diagram of segments. We also introduce the min-max Voronoi diagram of rectangles, a combinatorial structure of independent interest. The critical area problem for breaks and via blocks is reduced to variations of weighted L Voronoi diagram of segments. Plane sweep algorithms to compute the appropriate Voronoi diagrams for each case are presented. As a result, the critical area for breaks and via blocks on a single layer can be computed accurately in one pass of the layout. The time complexity is O(n log n) in the case of breaks and O((n+K)log n) in the case of via blocks, where n is the size of the input and K is upper-bounded by the number of interacting vias (in practice K is small). The critical area computation assumes square defects and reflects all possible defect sizes following the D(r)=r02/r3 defect size distribution. The method is presented for rectilinear layouts

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:20 ,  Issue: 5 )