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Look-ahead input buffer and dynamic load sensing scheme for 3.3 V ultrafast BiCMOS SRAMs

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8 Author(s)
Jung, C.M. ; Product Dev. Center, Samsung Electron. Co. Ltd., Seoul, South Korea ; Park, H.C. ; Ahn, K.S. ; Lee, J.H.
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Achieving fast access time at low voltage and low power is still a demanding task for high density SRAM. Although some previous BiCMOS designs operate at 3.3 V, the access time is usually slower than at 5 V. The speed is mainly dependent on the I/O interface conversion and delay due to long data lines. We developed a look-ahead input buffer to reduce the speed delay at the input stage and a dynamic load sensing scheme to minimize the sensing delay due to long data line. A 3.3 V 1 Mbit(l28K x 8) SRAM is designed to achieve 4.5 ns access time under typical conditions using 0.5 /spl mu/m BiCMOS technology.

Published in:

VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on

Date of Conference:

19-21 May 1993