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A distributed globally replaceable redundancy scheme for sub-half micron ULSI memories and beyond

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5 Author(s)
Sato, H. ; LSI Lab., Mitsubishi Electr. Corp., Itami, Japan ; Yamagata, T. ; Fujita, K. ; Nisimura, Y.
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A Distributed Globally Replaceable Redundancy (DGR) scheme has been developed, which realizes a higher optimization of trade-off between yield and chip size. A newly developed yield simulator has demonstrated the effectiveness of the DGR scheme.

Published in:

VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on

Date of Conference:

19-21 May 1993