By Topic

Bidirectional matched global bit line scheme for high density DRAMs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Ahn, J.H. ; Res. & Dev. Lab., GoldStar Electron Co. Ltd., Seoul, South Korea ; Kim, T.H. ; Park, S.M. ; Wang, S.H.
more authors

A new bit line organization, called Bidirectional Matched Global Bit Line (BMGB) scheme, is designed to overcome the difficulties in layout implementation and the high susceptibility to noise of conventional open bit line structure. In this scheme, the local bit line pairs are placed close to each other and well-balanced folded bit line type global bit lines are used. Measured results from a test chip, processed with 0.35 /spl mu/m technology, shows that cell array size can be reduced about 15%, while a similar performance is obtained to that of a conventional folded bit line architecture. This scheme can also be used with folded type local bit lines.

Published in:

VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on

Date of Conference:

19-21 May 1993