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A new bit line organization, called Bidirectional Matched Global Bit Line (BMGB) scheme, is designed to overcome the difficulties in layout implementation and the high susceptibility to noise of conventional open bit line structure. In this scheme, the local bit line pairs are placed close to each other and well-balanced folded bit line type global bit lines are used. Measured results from a test chip, processed with 0.35 /spl mu/m technology, shows that cell array size can be reduced about 15%, while a similar performance is obtained to that of a conventional folded bit line architecture. This scheme can also be used with folded type local bit lines.