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Low power self refresh mode DRAM with temperature detecting circuit

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7 Author(s)
Kagenishi, Y. ; Memory Div., Matsushita Electron. Corp., Nagaokakyo, Japan ; Hirano, H. ; Shibayama, A. ; Kotani, H.
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To reduce self refresh mode current, a temperature detecting circuit, back bias generator and voltage down convertor, are developed. Using these circuits in a 16M DRAM, 33 /spl mu/A consuming current in self refresh mode has been realized at Vcc=5V, Ta=25 /spl deg/C.

Published in:

VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on

Date of Conference:

19-21 May 1993

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