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A digital neuroprocessor using quantizer neurons

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9 Author(s)
H. Nakahira ; Matsushita Electr. Ind. Co. Ltd., Moriguchi, Japan ; S. Sakiyama ; M. Maruyama ; K. Hasegawa
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We discuss a digital neuroprocessor using quantizer neurons designed for character or image recognition and learning. The number of synapses in a neural network is a very important factor for the accurate recognition of images. A neural network with a large amount of synapses can achieve high recognition accuracy, however, it makes the processing speed lower because of the large number of network calculations. To realize both a large amount of synapses and high speed processing, a neuroprocessor has been fabricated with the Multi-Functional Layered Network (MFLN) model. The neuroprocessor contains 27,000 gates on a chip fabricated by using 1.2 /spl mu/m double metal CMOS, sea of gates technology. Chip size is 10.99 mm x 10.93 mm. The neuroprocessor operates with a clock cycle time of 25 nsec. It simulates the MFLN model with 4,736 neurons and two million synaptic weights in 2.8 msec when the width of the combination function is three. Therefore, the performance is 0.76 GCPS (Giga Connections Per Second). It achieves 20.5 GCPS, when the width of the combination function is one. It can execute Hebbian learning with 20.0 MCUPS (Mega Connections Updated Per Second).

Published in:

VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on

Date of Conference:

19-21 May 1993