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A method of measuring digital noise in an analog circuit such as an A/D converter by a voltage comparator is proposed and the noise dependence was measured by a fabricated test chip. For mixed-signal ICs, it was shown that the effect of digital noise can be considerably reduced by using a differential configuration in analog circuits. The effect of digital noise can be further reduced by lowering the digital supply voltage. This can be achieved by lowering the supply voltage to the extent of the speed requirements of digital currents while keeping the analog supply voltage high enough to meet the required signal-to-noise ratio.