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A CMOS 50 MHz CISC superscalar microprocessor

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20 Author(s)
Arakawa, F. ; Central Res. Lab., Hitachi Ltd., Tokyo, Japan ; Uchiyama, K. ; Aoki, H. ; Narita, S.
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Describes a CISC superscalar microprocessor. It executes 126 instructions with 14 addressing modes, which include floating-point processing fully compatible with the ANSI/IEEE 754-1985 standard. A 64-entry branch-always target buffer (BTB) enables O-cycle branching. An 8-entry return buffer (RB) reduces execution cycles of returns from a subroutine. The processor incorporates 8-kB instruction and operand physical caches (IC and OC), 64-entry instruction and operand translation look-aside buffers (ITLB and OTLB), and a 4-entry store buffer (SB). We focus on two problems particular to adopting a superscalar architecture with a variable-length CISC instruction set. These are: 1) how to dispatch two variable-length instructions per cycle; 2) how to implement complicated operation instructions.

Published in:

VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on

Date of Conference:

19-21 May 1993

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