By Topic

Design of digital filters for advanced telecommunications ASIC's using a special-purpose silicon compiler

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Balestro, F. ; France Telecom, CNET, Meylan, France ; Chianale, A. ; Privat, G. ; Tawfik, M.S.
more authors

Complex DSP (digital signal processor) ASICs (application-specific integrated circuits) typically feature high-quality filters implemented as dedicated blocks. FIDYS (filter 1di synthesis system) is a new VLSI recursive filter compiler, specifically designed to meet those needs. It is fully integrated from behavioral frequency template specifications down to layout. It comprises a specific approximation and synthesis procedure, the generation of a systolic architecture with parameterized pipelining based on dedicated bit-serial operators, and final generation of a densely packed layout based on a minimal dedicated set of 1-μm CMOS basic cells. A lossless discrete integrator ladder filter structure is used. It features an outstanding low sensitivity and a high degree of modularity and regularity that directly result in streamlined hardware and an efficient placement with minimal routing overhead. Examples of representative applications for telecommunications circuits are presented

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:26 ,  Issue: 7 )