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1 V input sampling circuit with improved linearity

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2 Author(s)
Chang, D. ; Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA ; Moon, U.

A highly linear low-voltage sampling circuit is proposed. Operation under 1 V power supply is possible without compromising linearity. Performance limiting nonlinear MOS switch resistance characteristics are suppressed by a combination of three novel design techniques

Published in:

Electronics Letters  (Volume:37 ,  Issue: 8 )

Date of Publication:

12 Apr 2001

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