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A mixed-signal approach to high-performance low-power linear filters

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3 Author(s)
W. Figueroa ; Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA ; D. Hsu ; C. Diorio

We present a new approach to the design of high-performance low-power linear filters. We use p-channel synapse transistors as analog memory cells, and mixed-signal circuits for fast low-power arithmetic. To demonstrate the effectiveness of our approach, we have built a 16-tap 7-b 200-MHz mixed-signal finite-impulse response (FIR) filter that consumes 3 mW at 3.3 V. The filter uses synapse pFETs to store the analog tap coefficients, electron tunneling and hot-electron injection to modify the coefficient values, digital registers for the delay line, and multiplying digital-to-analog converters to multiply the digital delay-line values with the analog tap coefficients. The measured maximum clock speed is 225 MHz; the measured tap-multiplier resolution is 7 b at 200 MHz. The total die area is 0.13 mm2. We can readily scale our design to longer delay lines

Published in:

IEEE Journal of Solid-State Circuits  (Volume:36 ,  Issue: 5 )