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A dual-loop delay-locked loop using multiple voltage-controlled delay lines

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6 Author(s)
Yeon-Jae Jung ; Sch. of Electr. Eng., Seoul Nat. Univ., South Korea ; Seung-Wook Lee ; Daeyun Shim ; Kim, Wonchan
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This paper describes a dual-loop delay-locked loop (DLL) which overcomes the problem of a limited delay range by using multiple voltage-controlled delay lines (VCDLs). A reference loop generates quadrature clocks, which are then delayed with controllable amounts by four VCDLs and multiplexed to generate the output clock in a main loop. This architecture enables the DLL to emulate the infinite-length VCDL with multiple finite-length VCDLs. The DLL incorporates a replica biasing circuit for low-jitter characteristics and a duty cycle corrector immune to prevalent process mismatches. A test chip has been fabricated using a 0.25-μm CMOS process. At 400 MHz, the peak-to-peak jitter with a quiet 2.5-V supply is 54 ps, and the supply-noise sensitivity is 0.32 ps/mV

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Solid-State Circuits, IEEE Journal of  (Volume:36 ,  Issue: 5 )