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A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector

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2 Author(s)
Savoj, J. ; Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA ; Razavi, B.

A 10-Gb/s phase-locked clock and data recovery circuit incorporates an interpolating voltage-controlled oscillator and a half-rate phase detector. The phase detector provides a linear characteristic while retiming and demultiplexing the data with no systematic phase offset. Fabricated in a 0.18-μm CMOS technology in an area of 1.1×0.9 mm2, the circuit exhibits an RMS jitter of 1 ps, a peak-to-peak jitter of 14.5 ps in the recovered clock, and a bit-error rate of 1.28×10-6, with random data input of length 223-1. The power dissipation is 72 mW from a 2.5-V supply

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:36 ,  Issue: 5 )