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On a dual-polarity on-chip electrostatic discharge protection structure

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2 Author(s)
Wang, A.Z.H. ; Integrated Electron. Lab., Illinois Inst. of Technol., Chicago, IL, USA ; Chen-Hui Tsay

A novel dual-polarity on-chip electrostatic discharge (ESD) protection structure is designed. The new ESD structure protects IC chips against ESD stressing in the two opposite directions. The ESD structure features symmetric deep-snapback current-voltage (I-V) characteristics, low-impedance active overcurrent discharging path, low holding voltage for overvoltage clamping, fast ESD response of ~0.18 ns, low leakage (~pA), adjustable triggering voltage, and good scalability. It passes 14 KV HBM ESD zapping tests and achieves high ESD-performance-to-Si ratio of ~80 V/μm width. The new ESD structure reduces Si areas consumed by ESD protection units and ESD-induced parasitic effects significantly

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Electron Devices, IEEE Transactions on  (Volume:48 ,  Issue: 5 )