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Sub-50 nm P-channel FinFET

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14 Author(s)
Xuejue Huang ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; Wen-Chin Lee ; Kuo, C. ; Hisamoto, D.
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High-performance PMOSFETs with sub-50-nm gate-length are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects. This vertical double-gate SOI MOSFET features: 1) a transistor channel which is formed on the vertical surfaces of an ultrathin Si fin and controlled by gate electrodes formed on both sides of the fin; 2) two gates which are self-aligned to each other and to the source/drain (S/D) regions; 3) raised S/D regions; and 4) a short (50 nm) Si fin to maintain quasi-planar topology for ease of fabrication. The 45-nm gate-length p-channel FinFET showed an Idsat of 820 μA/μm at Vds=Vgs=1.2 V and T ox=2.5 mm. Devices showed good performance down to a gate-length of 18 nm. Excellent short-channel behavior was observed. The fin thickness (corresponding to twice the body thickness) is found to be critical for suppressing the short-channel effects. Simulations indicate that the FinFET structure can work down to 10 nm gate length. Thus, the FinFET is a very promising structure for scaling CMOS beyond 50 nm

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Electron Devices, IEEE Transactions on  (Volume:48 ,  Issue: 5 )