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Bit-fixing in pseudorandom sequences for scan BIST

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2 Author(s)
N. A. Touba ; Dept. of Electr. Eng., Stanford Univ., CA, USA ; E. J. McCluskey

A low-overhead scheme for achieving complete (100%) fault coverage during built-in self test of circuits with scan is presented. It does not require modifying the function logic and does not degrade system performance (beyond using scan). Deterministic test cubes that detect the random-pattern-resistant (r.p.r.) faults are embedded in a pseudorandom sequence of bits generated by a linear feedback shift register (LFSR). This is accomplished by altering the pseudorandom sequence by adding logic at the LFSR's serial output to “fix” certain bits. A procedure for synthesizing the bit-fixing logic for embedding the test cubes is described. Experimental results indicate that complete fault coverage can be obtained with low hardware overhead. Further reduction in overhead is possible by using a special correlating automatic test pattern generation procedure that is described for finding test cubes for the r.p.r. faults in a way that maximizes bitwise correlation

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:20 ,  Issue: 4 )